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january 2014 exar corporation 48720 kato road, fremont ca 94538, usa general description the xrp7725 is a quad channel digital pulse width modulated (dpwm) step down (buck) controller. a wide 4.75v to 5.5v and 5.5v 25v input voltage dual range allows for supply operation from standard power rails. with integrated fet gate drivers, two ldos for standby power and a 105khz to 1.23mhz independent channel to channel programmab constant operating frequency , the xrp772 reduces overall component count footprint and optimizes conversion efficiencies. a selectable digital pulse frequency mode (dpfm) and low operating current result in better than 80% efficiency down to 10ma load provides support for portable and energy star compliant applications. each xrp7725 channel is individually programmable a minimum 0.6v with a resolution and configurable for precise soft start and soft stop sequencing, including delay and ramp control. the xrp7725 operation is fully controlled an smbus-compliant i 2 c interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as well as fault handling. built-in independent output over voltage, over temperature, over- current and under voltage lockout protections insure safe operation under abnormal operating conditions. the xrp7725 is offered in a rohs compliant, green/halogen free 44- pin tqfn package. typical application diagram figure i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 48720 kato road, fremont ca 94538, usa tel. +1 510 668-7000 C fax. +1 510 668 digital pulse step down (buck) to 5.5v and 5.5v to range allows for single supply operation from standard power rails. with integrated fet gate drivers, two ldos for standby power and a 105khz to 1.23mhz independent channel to channel programmab le , the xrp772 5 and solution conversion efficiencies. a selectable digital pulse frequency mode and low operating current result in better than 80% efficiency down to 10ma load provides support for portable and energy star xrp7725 output programmable down to with a resolution of 2.5mv, and configurable for precise soft start and soft stop sequencing, including delay and ramp controlled via c interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as output over voltage, over current and under voltage lockout protections insure safe operation under abnormal operating conditions. is offered in a rohs compliant, pin tqfn package. features ? quad channel step- down c ? digital pwm 105khz- 1.23mhz ? individual channel frequency selection ? patented digital pfm with ? patented over sampling feedback ? instanta neous current monitoring intel ? node manager compatible ? 4.75v to 25v input voltage ? 4.75v-5.5v and 5.5v- 25v input ranges ? 0.6v to 5.5v output voltage ? smbus compliant - i 2 c int ? full power monitoring and reporting ? 3 x 15v capable psio + 2 ? full start/stop sequencing support ? built- in thermal, over and output over- voltage protections ? on board 5v and 3.3v standby ldos ? on board non- volatile ? supported by powerarchitect applications ? blade servers ? micro servers ? network adapter cards ? base stations ? switches/routers ? broadcast equipment ? industrial control systems ? automatic test equipment diagram figure 1: xrp7725 application diagram xrp7725 x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 www.exar.com fax. +1 510 668 -7001 down c ontroller 1.23mhz operation channel frequency selection with ultrasonic mode patented over sampling feedback neous current monitoring C compatible to 25v input voltage 25v input ranges voltage c int erface full power monitoring and reporting 3 x 15v capable psio + 2 x gpios full start/stop sequencing support in thermal, over -current, uvlo voltage protections and 3.3v standby ldos volatile memory powerarchitect ? 5 network adapter cards industrial control systems automatic test equipment
i i n n t t e e l l ? 2012 exar corporation confidential features and benefits programmable power benefits ? fully configurable ? output set point ? feedback compensation ? frequency set point ? under voltage lock out ? input voltage measurement ? gate drive dead time ? reduced development time ? configurable and re- configurable for different vout, iout, cout, and inductor values ? no n eed to change external passives for a new output specification. ? higher integration and reliability ? many external component s used in the past can be eliminated thereby significantly improving reliability. powerarchitect? 5.1 design and configuration software ? wizard quickly generates a base design ? calculates all configuration registers ? projects can be saved and/or recalled ? gpios can be configured easily and intuitively ? dashboard i nterface can be used for real time monitoring and debug system benefits ? i ntel node manager compatible current monitoring. ? ability to perform remote configuration updates. ? ability to analyze operating history, perform diagnostics and if required, take the supply off- line after making other system adjustments. n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p r r o o g g r r a a m m m m a a n n a a g g 2/34 programmable power benefits configurable for different vout, iout, cout, and inductor eed to change external passives for a higher integration and reliability s used in the past can be eliminated thereby significantly improving reliability. powerarchitect? 5.1 design and wizard quickly generates a base design calculates all configuration registers projects can be saved and/or recalled gpios can be configured easily and nterface can be used for real - ntel node manager compatible current ability to perform remote configuration analyze operating history, perform diagnostics and if required, take the supply line after making other system system integratio n capabilities ? single supply operation ? i 2 c interface allows: ? intel node manager compatible as well as other power management systems ? modification or read ing of registers that control or monitor: ? output current ? input and output voltage ? soft-start/soft- stop time ? power good ? part temperature ? enable/disable outputs ? over current ? over voltage ? temperature faults ? adjusting fault limits and disabling/enabling faults ? packet error checking (pec) on i communication ? 5 gpio pins with a wide range of configurability ? fault reporting (including uvlo warn/fault, ocp warn/fault, ovp, temperature, soft- start in progress, power good, system reset) ? allows a logic level interface with other non- digital ics or as logic inputs to other devices ? frequency and syn chronization capability ? selectable switching frequency between 105khz and 1.2mhz ? main oscillator clock and dpwm clock can be synchronized to external sources ? master, slave and stand configurations are possible ? internal mosfet drivers ? internal f et drivers (4m/2m) per channel ? built- in automatic dead ? 30ns rise and fall times ? 4 independent smps channels and 2 ldos in a 7x7mm tqfn x x r r p p 7 7 7 7 2 2 5 5 m m m m a a b b l l e e p p o o w w e e r r g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 n capabilities single supply operation intel node manager compatible as well as other power management systems ing of internal registers that control or monitor: input and output voltage stop time enable/disable outputs adjusting fault limits and disabling/enabling faults packet error checking (pec) on i 2 c 5 gpio pins with a wide range of fault reporting (including uvlo warn/fault, ocp warn/fault, ovp, start in progress, power good, system reset) allows a logic level interface with other digital ics or as logic inputs to other chronization selectable switching frequency between main oscillator clock and dpwm clock can be synchronized to external sources master, slave and stand -alone configurations are possible internal mosfet drivers et drivers (4m/2m) per channel in automatic dead -time adjustment 30ns rise and fall times 4 independent smps channels and 2 ldos in a 7x7mm tqfn
? 2014 exar corporation absolute maximum rat ings these are stress ratings only and functional operat ion of the device at these ratings or any other above thos e indicated in the operation sections of the specific ations below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. vccd, ldo5, ldo3_3, glx, voutx ............. enable, 5v_ext ................................ ....... gpio0/1, scl, sda ................................ ............... psios inputs, bfb ................................ .................. dvdd, avdd ................................ ........................ v cc ................................ ................................ lx# ................................ ............................. bstx, ghx ................................ .................... storage temperature .............................. junction temperature ................................ power dissipation ................................ internally limited lead temperature (soldering, 10 sec) ................... esd rating (hbm - human body model) .................... electrical specifica tions specifications with standard type are for an operat ing junction temperature of t operating junction temperature range are denoted by a ?. = 25c, and are provided for reference purposes onl y. unless otherwise indicated, v q uiescent c urrent parameter min. v cc supply current in shutdown enable turn on threshold 0 .82 enable pin leakage current -10 v cc supply current in standby v cc supply current 2ch pfm v cc supply current 4ch pfm v cc supply current on i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 3/34 ings these are stress ratings only and functional operat ion of the device at these ratings or any other above thos e indicated in the operation sections of the specific ations below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect ............. -0.3v to 7.0v ....... -0.3v to 7.0v ............... 6.0v .................. 18v ........................ 2.0v ................................ ....... 28v ............................. -1v to 28v .................... vlxx + 6v -65c to 150c ................................ .......... 150c internally limited ................... 300c .................... 2kv operating ratings input voltage range v cc ............................... input voltage range v cc = ldo5 ................ vout1, 2, 3, 4 ................................ junction temperature range .................... jedec thermal resistance ja .......................... tions specifications with standard type are for an operat ing junction temperature of t j = 25c only; limits applying over the full operating junction temperature range are denoted by a ?. typical values represen t the most likely parametric norm at t = 25c, and are provided for reference purposes onl y. unless otherwise indicated, v cc = 5.5v to 25v, 5v ext open min. typ. max. units conditions 10 20 va en = 0v, v cc = 12v .82 0.95 v v cc = 12v enable rising 10 ua en=5v ua en=0v 440 600 va ldo3_3 disabled, all channels disabled gpios programmed as v cc =12v,en = 5v 3.1 ma 2 channels on and to 5.1v, no load, non sonic off, v cc =12 v, no i 4.0 ma 4 channels on and to 5.1v, no load, non sonic off, v cc =12v 18 ma all channels enabled, drivers unloaded , no i x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 ............................... 5.5v to 25v ................ 4.75v to 5.5v ................................ ...................... 5.5v .................... -40c to 125c .......................... 30.2c/w = 25c only; limits applying over the full t the most likely parametric norm at t j 25v, 5v ext open . conditions = 12v enable rising ldo3_3 disabled, all channels disabled gpios programmed as inputs =12v,en = 5v and set at 5v, vout forced to 5.1v, no load, non -switching, ultra- =12 v, no i 2 c activity. and set at 5v, vout forced to 5.1v, no load, non -switching, ultra- =12v , no i 2 c activity. all channels enabled, fsw=600khz, gate , no i 2 c activity.
? 2014 exar corporation i nput v oltage r ange and u ndervoltage parameter min. v cc range 5.5 4.75 v oltage f eedback a ccuracy and parameter min. vout regulation accuracy low output range 0.6v to 1.6v pwm operation -5 -20 -7.5 -22.5 vout regulation accuracy mid output range 0.6v to 3.2v pwm operation -15 -45 -20 -50 vout regulation accuracy high output range 0.6v to 5.5v pwm operation -30 -90 -40 -100 vout regulation range 0.6 vout native set point resolution vout fine set point resolution 1 vout input resistance vout input resistance in pfm operation power good and ovp set point range (from set point) -155 -310 -620 power good and ovp set point accuracy -5 -10 -20 bfb set point range 9 bfb set point resolution bfb accuracy -0.5 note 1: fine set point resolution not available in pfm i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 4/34 ndervoltage l ockout typ. max. units conditions 25 v ? 5.5 v ? with v cc c onnected to ldo5 ccuracy and o utput v oltage s et p oint r esolution typ. max. units conditions 5 mv 0.6 vout 1. 6 20 mv ? 7.5 mv 0.6 vout 1.6v v cc =ldo5 22.5 mv ? 15 mv 0.6 vout 3.2 45 mv ? 20 mv 0.6 vout 3.2 v cc =ldo5 50 mv ? 30 mv 0.6 vout 5.5v 90 mv ? 40 mv 0.6 vout 4.2v v cc =ldo5 100 mv ? 5.5 v ? without external divider network 12.5 25 50 mv low range mid range high range 2.5 5 10 mv low range mid range high range 120 90 75 kx low range mid range high range 10 1 0.67 mx low range mid range high range 157.5 315 630 mv low range mid range high range 5 10 20 mv low range mid range high range 16 v 1 v 0.5 v note 1: fine set point resolution not available in pfm x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 conditions onnected to ldo5 esolution conditions 6 v vout 1.6v 3.2 v 3.2 v vout 5.5v vout 4.2v without external divider network
? 2014 exar corporation c urrent and aux adc (m onitoring parameter min. typ. current sense accuracy -3.75 1.25 -10 -5 2.5 -12.5 current sense adc inl dnl 0.27 current limit set point resolution and current sense adc resolution 1.25 2.5 current sense adc range -120 -280 vout adc resolution 15 30 60 vout adc accuracy -1 v cc adc range 4.6 uvlo warn set 4.4 uvlo warn clear 4.4 uvlo fault set (note 3) 4.2 v cc adc resolution 200 v cc adc accuracy -1 die temp adc resolution die temp adc range -44 note 2: although range of v cc adc is 0v to 25v, note 3 : this test ensures an uvlo fault flag will be give n before the ldo5 hardware uvlo trips. l inear r egulators parameter min. ldo5 output voltage 4.85 ldo5 current limit 135 ldo5 uvlo 4.74 ldo5 pgood hysteresis ldo5 bypass switch resistance bypass switch activation threshold 2.5 bypass switch activation hysteresis ldo3_3 output voltage 3.15 ldo3_3 current limit 53 maximum total ldo loading during enable start-up i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 5/34 onitoring adc s ) typ. max. units conditions 1.25 3.75 mv low range (120mv) -60mv applied 10 mv ? 2.5 5 mv high range (280mv) -150mv +12.5 mv ? 0.4 lsb 0.27 1.25 mv low range (120mv) 2.5 mv high range (280mv) 20 mv low range (120mv) 40 high range (280mv) 15 30 60 mv low range mid range high range 1 lsb 25 v note 2 4.72 v uvlo warn set point 4.6v, 4.72 v uvlo warn set point 4.6v, 4.55 v uvlo fault set point 4.4v, 200 mv 1 lsb vin <= 20v 5 c 156 c output value is in kelvin adc is 0v to 25v, operation below 4.55 is not supported. : this test ensures an uvlo fault flag will be give n before the ldo5 hardware uvlo trips. typ. max. units conditions 5.0 5.15 v ? 5.5v v cc 25 0ma < i ldo5 out 155 180 ma ? ldo5 fault set v ? v cc rising 375 mv v cc falling 1.1 1.5 m 2.5 % ? v5ext rising , % of threshold setting 150 mv v5ext falling 3.3 3.45 v ? 4.6v ldo5 0ma < i ldo3_3out 85 ma ? ldo3_3 fault set 30 ma enable transition from logic low to high. once ldo5 in regulation above limits apply. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 conditions uvlo warn set point 4.6v, v cc =ldo5 uvlo warn set point 4.6v, v cc =ldo5 uvlo fault set point 4.4v, v cc =ldo5 output value is in kelvin conditions 25 v out < 130ma, ldo3_3 off ldo5 fault set , % of threshold setting ldo5 5.5v ldo3_3out < 50ma ldo3_3 fault set enable transition from logic low to high. once ldo5 in regulation above
? 2014 exar corporation pwm g enerators and o scillator parameter min. switching frequency (fsw) range 105 fsw accuracy C5 clock in synchronization frequency 20 clock in synchronization frequency 10 gpio s 4 parameter min. input pin low level input pin high level 2.0 input pin leakage current output pin low level output pin high level 2.4 output pin high level output pin high-z leakage current (gpio pins only) maximum sink current i/o frequency note 4: 3.3v cmos logic compatible, 5v tolerant psio s 5 parameter min. input pin low level input pin high level 2.0 input pin leakage current output pin low level output pin high level output pin high-z leakage current (psio pins only) i/o frequency note 5: 3.3v/5.0v cmos logic compatible, maximum rating of 15.0v i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 6/34 scillator typ. max. units conditions 1230 khz steps defined in t 5 % 25.7 31 mhz when synchronizing to an external clock (range 1) 12.8 15.5 mhz when synchronizing to an external clock (range 2) typ. max. units conditions 0.8 v v 1 va 0.4 v i sink = 1ma v i source = 1ma 3.3 3.6 v i source = 0ma 10 va 1 ma open drain mode 30 mhz 5v tolerant . typ. max. units conditions 0.8 v v 1 va 0.4 v i sink = 3ma 15 v open drain. external pull user supply 10 va 5 mhz 3.3v/5.0v cmos logic compatible, maximum rating of 15.0v x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 conditions t able 1 when synchronizing to an external clock synchronizing to an external clock conditions conditions external pull -up resistor to
? 2014 exar corporation smb us (i2c) i nterface parameter min. input pin low level, v il input pin high level, v ih 0.7 vio hysteresis of schmitt trigger inputs, v hys 0.05 v io output pin low level (open drain or collector), v ol input leakage current -10 output fall time from v ihmin to v ilmax 20 + 0.1 cb internal pin capacitance g ate d rivers parameter min. gh, gl rise time gh, gl fall time gh, gl pull-up on-state output resistance gh, gl pull-down on-state output resistance gh, gl pull-down resistance in off-mode bootstrap diode forward resistance minimum on time minimum off time minimum programmable dead time maximum programmable dead time programmable dead time adjustment step i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 7/34 typ. max. units conditions 0.3 vio v vio = 3.3 v 10% v vio = 3.3 v10% io v vio = 3.3 v10% 0.4 v i sink = 3ma 10 va input is between 0.1 20 + 0.1 250 ns w ith a bus capacitance 400 pf 1 pf typ. max. units conditions 17 ns at 10- 90% of full scale, 11 ns 4 5 x 2 2.5 x 50 kx v cc = vccd = 0v. 9 x @ 10ma 50 ns 1nf of gate capacitance. 125 ns 1nf of gate capacitance 20 ns does not include dead time variation from driver output stage tsw=switching period tsw us 607 ps x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 conditions = 3.3 v 10% = 3.3 v10% = 3.3 v10% input is between 0.1 vio and 0.9 vio ith a bus capacitance (cb) from 10 pf to conditions 90% of full scale, 1nf c load 0v. 1nf of gate capacitance. 1nf of gate capacitance include dead time variation from driver output stage tsw=switching period
? 2014 exar corporation block diagram ldo block diagram figure gpio 0-1 v ref dac prescaler 1/2/4 vout1 gpio i2c sda,scl vout3 vout4 psio 0-2 psio enable vout3 4ua i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 8/34 figure 2: xrp7725 block diagram figure 3: xrp7725 ldo block diagram bst1 channel 1 gh1 vcc gl1 lx1 gl_ rtn ldo5 hybrid dpwm digital pid feedback adc ss & pd current adc dead time gate driver vccd3- 4 channel 3 channel 4 mux vout1 vout2 vout3 vout4 vtj 5v ldo nvm (flash) clock pwr good configuration registers fault handling otp uvlo ocp ovp logic ldo3_3 3.3v ldo vccd1- 2 channel 2 sequencing internal por vcc bfb x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 rtn 1 4 2
? 2014 exar corporation pin assignment pin description name pin number v cc 41 input voltage. place a decoupling capacitor close t o the fault generation. dvdd 16 1.8v supply capacitor close to the vccd1-2 vccd3-4 23,34 gate drive supply. two independent gate drive suppl y pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. one of the two pins must be connected to the ldo5 pin to enable two power rails initially. it is recom the other vccd pin be connected to the output of a 5v switching efficiency or for driving larger external fets), if available, otherwise this pin may also be connected to the ldo5 pin. a bypass capacitor (>1uf) to pad is re each vccd pin with the pin(s) connected to ldo5 wit h shortest possible etch agnd 2 analog ground pin. this is the small signal ground connection. gl_rtn1-4 39,33, 28,22 ground connection for the low side gate driver. th is should be routed with gl. connect to the source of the low side mos fet. gl1-gl4 38,32, 27,21 output pin of the low side gate driver. connect dir ectly to the gate of an external n channel mosfet. gh1-gh4 36,30, 25,19 output pin of the high side gate dr channel mosfet. 1 3 12 10 1 2 3 4 5 6 7 8 9 4 3 44 ldo3_3 agnd cpll avdd vout1 vout2 vout4 gpio0 gpio1 scl p s i o 0 ldo5 v 5 e x t vout3 11 sda i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 9/34 figure 4: xrp7725 pin assignment description input voltage. place a decoupling capacitor close t o the pin . this input is used in uvlo fault generation. 1.8v supply input for digital circuitry. connect pin to avdd. place a decoupling capacitor close to the pin. gate drive supply. two independent gate drive suppl y pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. one of the two pins must be connected to the ldo5 pin to enable two power rails initially. it is recom the other vccd pin be connected to the output of a 5v switching efficiency or for driving larger external fets), if available, otherwise this pin may also be connected to the ldo5 pin. a bypass capacitor (>1uf) to pad is re each vccd pin with the pin(s) connected to ldo5 wit h shortest possible etch analog ground pin. this is the small signal ground connection. ground connection for the low side gate driver. th is should be routed with gl. connect to the source of the low side mos fet. output pin of the low side gate driver. connect dir ectly to the gate of an external n channel mosfet. output pin of the high side gate dr iver. connect directly to the gate of an external n channel mosfet. 33 32 31 30 29 28 27 26 24 25 20 19 17 18 16 15 1 3 14 36 37 39 38 40 41 4 3 42 21 35 gl2 lx2 gh2 bst2 gl_rtn gl3 lx3 gh3 bst3 vccd3- 4 psio1 psio2 dvdd p s i o 0 dgnd bst4 gh4 lx4 gl4 v 5 e x t bfb vcc enable gl1 lx1 gh1 bst1 vccd1-2 exposed pad: agnd xrp7725 tqfn 7mm x 7mm 23 gl_rtn 34 gl_rtn1 22 gl_rtn4 x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 . this input is used in uvlo for digital circuitry. connect pin to avdd. place a decoupling gate drive supply. two independent gate drive suppl y pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. one of the two pins must be connected to the ldo5 pin to enable two power rails initially. it is recom mended that the other vccd pin be connected to the output of a 5v switching rail (for improved efficiency or for driving larger external fets), if available, otherwise this pin may also be connected to the ldo5 pin. a bypass capacitor (>1uf) to pad is re commended for each vccd pin with the pin(s) connected to ldo5 wit h shortest possible etch . ground connection for the low side gate driver. th is should be routed as a signal trace output pin of the low side gate driver. connect dir ectly to the gate of an external n - iver. connect directly to the gate of an external n - 3 4 2
? 2014 exar corporation name pin number lx1-lx4 37,31, 26,20 lower supply rail for the gh high node at the junction between the two external power mosfets and the inductor. pins are also used to measure voltage drop across b ottom mosfets in order to provide output current information to the control engine. bst1-bst4 35,29, 24,18 high side driver supply pin(s). connect bst to the external capacitor as shown in the typical application circuit on page bst pin and lx pin and delivers the bst pin voltage to the high side fet gate each cycle. gpi0-gpio1 9,10 these pins can be configured as inputs or outputs t o implement custom flags, power good signals, enable/disable controls and synchroni zation to an external clock. psio0-psio2 13,14,15 open drain, these pins can be used to control ex on and off, shedding the load for fine grained powe r management. they can also be configures as standard logic outputs or inputs just as any of the gpios can be configured, but as open drains require an external pull sda, scl 11,12 smbus/i vout1-vout4 5,6,7,8 connect to the output of the corresponding power st age. the output is sampled at least once every switching cycle ldo5 44 output of a 5v ldo. this is a micro power ldo that can remain active while the rest of the ic is in blocks. ldo3_3 1 output of the 3.3v standby ldo. this is a micro pow er ldo that can while the rest of the ic is in shutdown. enable 40 if enable is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). the pin must be held low for the xrp772 placed into s bfb 42 input from the 15v output created by the external b oost supply. when this pin goes below a pre output back to the original level. if not used, th is pin should be dgnd 17 digital ground pin. this is the logic ground connec tion, and should be connected to the ground plane close to the pad. cpll 3 connect to a 2.2nf capacitor to gnd. v5ext 43 external 5v that can be provided. if one of the then this voltage can be fed back to this pin for r educed operating current of the chip and improved efficiency. avdd 4 output of the internal 1.8v ldo. a decoupling capa citor should be placed between avdd and agnd c pad 45 this is the die attach paddle, which is exposed on the bottom of the part. connect externally to the ground plane. ordering information part number temperature range xrp7725ilb-f -40ct j +125c xrp772 xrp7725ilbtr-f -40ct j +125c XRP7725EVB-DEMO-1-kit evaluation kit includes architect XRP7725EVB-DEMO-1 xrp7725 evaluation board yy = year C ww = work week i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 10/34 description lower supply rail for the gh high - side gate driver. connect this pin to the switching node at the junction between the two external power mosfets and the inductor. pins are also used to measure voltage drop across b ottom mosfets in order to provide output current information to the control engine. high side driver supply pin(s). connect bst to the external capacitor as shown in the typical application circuit on page 2 . the high side driver is connected between the bst pin and lx pin and delivers the bst pin voltage to the high side fet gate each these pins can be configured as inputs or outputs t o implement custom flags, power good signals, enable/disable controls and synchroni zation to an external clock. open drain, these pins can be used to control ex ternal power mosfets to switch loads on and off, shedding the load for fine grained powe r management. they can also be configures as standard logic outputs or inputs just as any of the gpios can be configured, but as open drains require an external pull -u p when configured as outputs. smbus/i 2 c serial interface communication pins. connect to the output of the corresponding power st age. the output is sampled at least once every switching cycle output of a 5v ldo. this is a micro power ldo that can remain active while the rest of the ic is in the stand-by mode . this ldo is also used to power the internal anal og output of the 3.3v standby ldo. this is a micro pow er ldo that can while the rest of the ic is in shutdown. if enable is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). the pin must be held low for the xrp772 placed into s hutdown. input from the 15v output created by the external b oost supply. when this pin goes below a pre - defined threshold, a pulse is created on the low si de drive to charge this output back to the original level. if not used, th is pin should be digital ground pin. this is the logic ground connec tion, and should be connected to the ground plane close to the pad. connect to a 2.2nf capacitor to gnd. external 5v that can be provided. if one of the output channels is configured for 5v, then this voltage can be fed back to this pin for r educed operating current of the chip and improved efficiency. output of the internal 1.8v ldo. a decoupling capa citor should be placed between avdd and agnd c lose to the chip. this is the die attach paddle, which is exposed on the bottom of the part. connect externally to the ground plane. marking package packing quantity note 1 xrp772 5ilb yyww lot # 44-pin tqfn 260/tray halogen free 2.5k/tape & reel halogen free evaluation kit includes XRP7725EVB-DEMO-1 evaluation board architect software and xrp77xxevb-xcm (usb to i 2 c exar configuration module) xrp7725 evaluation board x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 side gate driver. connect this pin to the switching node at the junction between the two external power mosfets and the inductor. these pins are also used to measure voltage drop across b ottom mosfets in order to provide high side driver supply pin(s). connect bst to the external capacitor as shown in the . the high side driver is connected between the bst pin and lx pin and delivers the bst pin voltage to the high side fet gate each these pins can be configured as inputs or outputs t o implement custom flags, power good signals, enable/disable controls and synchroni zation to an external clock. ternal power mosfets to switch loads on and off, shedding the load for fine grained powe r management. they can also be configures as standard logic outputs or inputs just as any of the gpios can be p when configured as outputs. connect to the output of the corresponding power st age. the output is sampled at least output of a 5v ldo. this is a micro power ldo that can remain active while the rest of . this ldo is also used to power the internal anal og output of the 3.3v standby ldo. this is a micro pow er ldo that can remain active if enable is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). the pin must be held low for the xrp772 5 to be input from the 15v output created by the external b oost supply. when this pin goes defined threshold, a pulse is created on the low si de drive to charge this connected to gnd. digital ground pin. this is the logic ground connec tion, and should be connected to the output channels is configured for 5v, then this voltage can be fed back to this pin for r educed operating current of the chip output of the internal 1.8v ldo. a decoupling capa citor should be placed between this is the die attach paddle, which is exposed on the bottom of the part. connect note 1 i 2 c default address halogen free 0x28 (7bit) halogen free evaluation board with power exar configuration module)
? 2014 exar corporation typical performance characteristics all data taken at v cc = 12v, t j = t a = 25c, unless otherwise XRP7725EVB-DEMO-1 manual. figure 5 : pfm to pwm transition figure 2: 0- 6a transient 300khz pwm only figure 4: sequential start- up i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 11/34 characteristics = 25c, unless otherwise specified - schematic and bom from : pfm to pwm transition figure 1: pwm to pf m transition 6a transient 300khz pwm only figure 3: 0- 6a transient 300khz with ovs 5.5% up figure 5: sequential shut down x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 schematic and bom from xrp7725evb. see m transition 6a transient 300khz with ovs 5.5% shut down
? 2014 exar corporation figure 6: simultaneous start figure 8 : pfm zero current accuracy figure 10: enable threshold over 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 - 40 c 25 c 85 c 125 c example i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 12/34 simultaneous start -up figure 7: simultaneous shut down : pfm zero current accuracy figure 9 : ldo5 brown out recovery, no load enable threshold over temp c vin=25v rising vin=25v falling vin=4.75 v rising vin=4.75 v falling vcc vcc vcc vcc x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 shut down : ldo5 brown out recovery, no load
? 2014 exar corporation functional overview the xrp7725 is a quad- output digital pulse width modulation (dpwm) controller with integrated gate drivers for use with synchronous buck switching regulators. each output voltage can be programmed from 0.6v to 5.5v without the need for voltage divider. the wide range of programmable dpwm switching frequency (from 105 khz to 1.2 mhz) enables the user to optimize for efficiency or component sizes. since t he digital regulation loop requires no external passive components, performance is not compromised due to external component variation or condition. the xrp7725 provides a number of critical safety features, such as over protection (ocp), over- voltage protection (ovp), over temperature protection (otp) plus input under voltage locko ut (uvlo). in addition, a number of key health monitoring features such as warning level flags for the safety functions, power goods ( pgood plus full monitoring of system voltages and currents. the above are all programmable and/or readable from the smbus and many are steerable to the gpios for hardware monitoring. for hardware communication, the xrp772 has two logic level general purpose input output (gpio) pins and three, 15v, open drain, power system input- output (psio) pins. two pins are dedicated to the smbus data (sda) and clock (scl). additional pins include chip enable (enable), aux boost feedback (bfb) and external pll capacitor (cpll). in addition to providing four switching outputs the xrp7725 also provides control for an boost supply, and two stand regulators that produce 5v and 3.3v of seven customer usab le supplies device. the 5v ldo is used for internal power and is also available for customer use to power i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 13/34 output digital pulse width modulation (dpwm) controller with integrated gate drivers for use with synchronous buck switching regulators. each output voltage can be programmed from 0.6v for an external voltage divider. the wide range of programmable dpwm switching frequency (from 105 khz to 1.2 mhz) enables the user to optimize for efficiency or component sizes. he digital regulation loop requires no components, loop is not compromised due to external component variation or operating provides a number of critical safety features, such as over -current voltage protection protection (otp) ut (uvlo). in addition, a number of key health monitoring features such as warning level flags for the pgood ), etc., full monitoring of system voltages and are all programmable smbus and many are steerable to the gpios for hardware for hardware communication, the xrp772 5 has two logic level general purpose input - output (gpio) pins and three, 15v, open output (psio) pins. two pins are dedicated to the smbus data (sda) and clock (scl). additional pins (enable), aux boost external pll capacitor four switching outputs , control for an aux two stand -by linear 3.3v for a total le supplies in a single the 5v ldo is used for internal power and is also available for customer use to power external circuitry. the 3.3v ldo is solely for customer use and is not used by the chip. there is also a 1.8v linear for internal use only and should not be used externally. a key feature of the xrp772 power management capabilities. all four outputs are independently programmable and provide the user full control of the ramp, and s equence during power up and power down. the user may also the outputs interact and power down in the event of a fault. this includes active ramp down of the output voltages to remove an output voltage as quickly as possible. another useful feature is that the defined and controlled as groups. the xrp7725 has two programmable memory. the first type runtime registers that contain configuration, control and monitoring information for the chip. the second type is rewritable non volatile flash memory (nv fm permanent storage of the configuration data along with various chip internal during power up, the run time registers are loaded from the nvfm allowing for operation. the xrp7725 brings an extreme functionality and performance programmable power system decreasing product budgets require the designer to quickly cost/performance tradeoff successful. by incorporating channels, two user ldos, a boost controller, along with internal gate drivers, all in a single package, allows for extremely cost effective power system designs. another key cost factor is often overlooked is the unanticipated engineering change order ( programmable versatility of the xrp772 along with the lack of hard wired configuration components, allows for minor and major changes to be made in circuit reprogramming. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 external circuitry. the 3.3v ldo is solely for customer use and is not used by the chip. linear regulator which is use only and should not be used a key feature of the xrp772 5 is its advinced power management capabilities. all four outputs are independently programmable and the user full control of the delay, equence during power up and the user may also control how the outputs interact and power down in the this includes active ramp down of the output voltages to remove an output voltage as quickly as possible. another the outputs can be defined and controlled as groups. has two main types of memory. the first type is runtime registers that contain configuration, control and monitoring information for the chip. the second type is rewritable non - fm ) that is used for permanent storage of the configuration data along with various chip internal functions. the run time registers are allowing for standalone extreme ly high level of functionality and performance to a programmable power system . ever decreasing product budgets require the quickly make good cost/performance tradeoff s to be truly successful. by incorporating four switching channels, two user ldos, a charge pump boost controller, along with internal gate drivers, all in a single package, the xrp7725 allows for extremely cost effective power another key cost factor that is the unanticipated engineering change order ( eco). the programmable versatility of the xrp772 5, along with the lack of hard wired configuration components, allows for minor and major changes to be made in circuit by simple
? 2014 exar corporation theory of operation c hip a rchitecture r egulation l oops error amp vref dac scaler 1,2,4 window comp. vfb (voutx) afe figure 16 shows a simplified functional block diagram of the regulation loops for channel of the xrp7725 . there are four separate parallel control loops; pulse width modulation (pwm), pulse frequency modulation (pfm), ultrasonic, and over sampling (ovs). each of these loops is fed by the analog front end (afe) as shown at the left of the diagram. the afe consist of an input voltage scaler, a programmable voltage reference (vref) dac, error amplifier, and a window comparator. some of the functional blocks are common and shared by each cha nnel by means of a multiplexer. pwm loop the pwm loop operates in voltage control mode (vcm) with optional v in feed forward based on the voltage at the v reference voltage (vref) for the error amp is generated by a 0.15v to 1.6v dac that has 12.5mv resolution. in order to provide a 0.6v to 5.5v output voltage range, an input scaler is used to reduce f eedback voltages for higher output voltages to bring them within the 0.15v to 1.6v control range. so for output voltages up to 1.6v (low range) the scaler has a gain of i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 14/34 afe adc error register pid dpwm pfm/ ultrasonic vin feed forward ovs vin (vcc) fine adjust figure 16: xrp7725 regulation loops functional block diagram of the regulation loops for one output . there are four control loops; pulse width modulation (pwm), pulse frequency modulation (pfm), ultrasonic, and over sampling (ovs). each of these loops is fed by the analog front end (afe) as shown at the left of the diagram. the afe consist of an programmable voltage reference (vref) dac, error amplifier, and a window comparator. some of the functional blocks are common and shared by each nnel by means of a multiplexer. the pwm loop operates in voltage control feed forward based on the voltage at the v cc pin. the reference voltage (vref) for the error amp is generated by a 0.15v to 1.6v dac that has 12.5mv resolution. in order to provide a 0.6v to 5.5v output voltage range, an input scaler eedback voltages for higher output voltages to bring them within the 0.15v to 1.6v control range. so for output voltages up to 1.6v (low range) the scaler has a gain of 1. for output voltages from 1.6v to 3.2v (mid range) the scaler gain is 1/2 and for vol greater than 3.2v (high range) the gain is 1/4. this results in the low range having a voltage resolution of 12.5mv, the mid range having a resolution of 25mv and the high range having a resolution of 50mv. the error amp has a gain of 4 and c ompares the output voltage of the scaler to vref to create an error voltage on its output. this is converted to a digital error term by the afe adc and is stored in the error register. the error register has a fine adjust function that can be used to impro ve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mv, a mid range resolution of 5mv and a high range resolution of 10mv. the output of the error register is then used by the proportional integral derivative (pid) controller to manage the loop dynamics. the xrp7725 pid is a 17 control engine that calculates the required duty cycle under the various operating conditions and feeds it to the digital pulse width modulator (dpwm). besides t x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 gate driver ghx glx lxx pwm- pfm sel current adc vdrive (vccd)x 1. for output voltages from 1.6v to 3.2v (mid range) the scaler gain is 1/2 and for vol tages greater than 3.2v (high range) the gain is 1/4. this results in the low range having a n output resolution of 12.5mv, the mid range having a resolution of 25mv and the high range having a resolution of 50mv. the error ompares the output voltage of the scaler to vref to create an error voltage on its output. this is converted to a digital error term by the afe adc and is stored in the error register. the error register has a fine adjust function that can be used to ve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mv, a mid range resolution of 5mv and a high range resolution of 10mv. the output of the error register is then used by the proportional integral (pid) controller to manage the loop pid is a 17 -bit five-coefficient control engine that calculates the required duty cycle under the various operating conditions and feeds it to the digital pulse width modulator (dpwm). besides t he normal
? 2014 exar corporation coefficients the pid also uses the v to provide a feed forward function. the xrp7725 dpwm includes a special delay timing loop that provides a timing resolution that is 16 times the master oscillator frequency (103mhz) for a timing reso 607ps for both the driver pulse width and dead time delays. the dwpm produces the gate high (gh) and gate low (gl) signals for the driver. the maximum and minimum on and dead time delays are programmable by configuration resisters. to prov ide current information, the output inductor current is measured by a differential amplifier that reads the voltage drop across the r ds of the lower fet during its on time. there are two selectable ranges, a low range with a gain of 8 for a +20mv to range, and a high range with a gain of 4 for a +40mv to - 280mv range. the optimum range to use will depend on the maximum output current and the r ds of the lower fet. the measured voltage is then converted to a digital value by the current adc block. the resulting current value is stored in a readable register, and also used to determine when pwm to pfm transitions should occur. pfm mode loop the xrp7725 has a pfm loop that can be enabled to improve efficiency at light loads. by reducing switching frequency and operating in the discontinuous conduction mode (dcm), both switching and conduction minimized. figure 17 shows a functional diagram o pfm logic. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 15/34 coefficients the pid also uses the v cc voltage to provide a feed forward function. dpwm includes a special delay timing loop that provides a timing resolution that is 16 times the master oscillator frequency (103mhz) for a timing reso lution of 607ps for both the driver pulse width and dead time delays. the dwpm produces the gate high (gh) and gate low (gl) signals for the driver. the maximum and minimum on -times and dead time delays are programmable by ide current information, the output inductor current is measured by a differential amplifier that reads the voltage drop across of the lower fet during its on time. there are two selectable ranges, a low range with a gain of 8 for a +20mv to -120 mv range, and a high range with a gain of 4 for a 280mv range. the optimum range to use will depend on the maximum output of the lower fet. the measured voltage is then converted to a digital value by the current adc block. the resulting current value is stored in a readable register, and also used to determine when pwm to pfm transitions should occur. has a pfm loop that can be enabled to improve efficiency at light loads. by reducing switching frequency and operating in the discontinuous conduction mode (dcm), losses are shows a functional diagram o f the # cycles reg default = 20 pfm current threshold reg a a ? 2014 exar corporation voltage ripple is well controlled and is much lower than in other architectures which use a burst methodology. if the output voltage goes outside the high/low windows , pfm mode is exited and the pwm loop is reactivated. although the pfm mode is effective at improving efficiency at light load, at very light loads the dead zone time can increase to the point where the switching frequency the audio hearing range. when this happens some components, like the output inductor and ceramic capacitors, can emit audible noise. the amplitude of the noise depends mainly on the board design and on the manufacturer and construction details components. proper selection of components can reduce the sound to very low levels. in general ultrasonic mode is not used unless required as it reduces light load efficiency. ultrasonic mode ultrasonic mode is an extension of pfm to ensure that th e switching frequency never enters the audible range. when this mode is entered, the switching frequency is set to 30khz and the duty cycle of the upper and lower fets, which are fixed in pfm mode, are decreased as required to keep the output voltage in re gulation while maintaining the 30khz switching frequency. under extremely light or zero load currents, the gh on time pulse width can decrease to its minimum width. when this happens, the lower fet on time is increased slightly to allow a small amount of reverse inductor current to flow back into v in to keep the output voltage in regulation while maintaining the switching frequency above the audio range. oversampling ovs mode oversampling (ovs) mode is a feature added to the xrp7725 to improve transient responses . this mode can only be enabled when the channel switching frequency is operating in 1x frequency mode. in ovs mode the output voltage is sampled four times per switching cycle and is monitored by the afe window comparators. if the voltage goes i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 16/34 voltage ripple is well controlled and is much other architectures which use a goes outside the , pfm mode is exited and the although the pfm mode is effective at improving efficiency at light load, at very light loads the dead zone time can increase to the point where the switching frequency can enter the audio hearing range. when this happens some components, like the output inductor and ceramic capacitors, can emit audible noise. the amplitude of the noise depends mainly on the board design and on the manufacturer and construction details of the components. proper selection of components can reduce the sound to very low levels. in general ultrasonic mode is not used unless required as it reduces light load efficiency. ultrasonic mode is an extension of pfm to e switching frequency never enters the audible range. when this mode is entered, the switching frequency is set to 30khz and the duty cycle of the upper and lower fets, which are fixed in pfm mode, are decreased as required to keep the output gulation while maintaining the under extremely light or zero load currents, the gh on time pulse width can decrease to its minimum width. when this happens, the lower fet on time is increased slightly to allow a reverse inductor current to to keep the output voltage in regulation while maintaining the switching oversampling (ovs) mode is a feature added to improve transient . this mode can only be enabled when the channel switching frequency is operating in 1x frequency mode. in ovs mode the output voltage is sampled four times per switching cycle and is monitored by the afe window comparators. if the voltage goes out side the set high or low limits, the ovs control electronics can immediately modify the pulse width of the gh or gl drivers to respond accordingly, without having to wait for the next cycle to start. ovs has two types of response depending on whether the h is exceeded during an unloading transient (over voltage), or the low limit is exceeded during a loading transient (under voltage). under voltage ovs: if there is an increasing current load step, the output voltage will drop until the regulato r loop adapts to the new conditions to return the voltage to the correct level. depending on where in the switching cycle the load step happens there can be a delay of up to one switching cycle before the control loop can respond. with ovs enabled if the o utput voltage drops below the lower level, an immediate gh pulse will be generated and sent to the driver to increase the output inductor current toward the new load level without having to wait for the next cycle to begin. if the output voltage is still b elow the lower limit at the beginning of the next cycle, ovs will work in conjunction with the pid to insert additional gh pulses to quickly return the output voltage back within its regulation band. the result of this system is transient response capabili exceeding those of a constant on loop. over voltage ovs: when there is a step load current decrease, the output voltage will increase (bump up) as the excess inductor current that is no longer used by the load flows into the out put capacitors causing the output voltage to rise. the voltage will continue to rise until the inductor current decreases to the new load current. with ovs enabled, if the output voltage exceeds the high limit of the window comparator, a blanking pulse is generated to truncate the gh signal. this causes inductor current to immediately begin decreasing to the new load level. the gh signal will continue to be blanked until the output voltage falls below the high limit. again, since the output voltage is sam pled at four times the switching frequency, over shoot will be decreased and the time required to get back into the regulation band is also decreased. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 side the set high or low limits, the ovs control electronics can immediately modify the pulse width of the gh or gl drivers to respond accordingly, without having to wait for the next cycle to start. ovs has two types of response depending on whether the h igh limit is exceeded during an unloading transient (over voltage), or the low limit is exceeded during a loading transient (under voltage). if there is an increasing current load step, the output voltage will drop r loop adapts to the new conditions to return the voltage to the correct level. depending on where in the switching cycle the load step happens there can be a delay of up to one switching cycle before the control loop can respond. with ovs enabled if utput voltage drops below the lower level, an immediate gh pulse will be generated and sent to the driver to increase the output inductor current toward the new load level without having to wait for the next cycle to begin. if the output voltage is still elow the lower limit at the beginning of the next cycle, ovs will work in conjunction with the pid to insert additional gh pulses to quickly return the output voltage back within the result of this system is transient response capabili ties on par or exceeding those of a constant on -time control when there is a step load current decrease, the output voltage will increase (bump up) as the excess inductor current that is no longer used by the load put capacitors causing the output voltage to rise. the voltage will continue to rise until the inductor current decreases to the new load current. with ovs enabled, if the output voltage exceeds the high limit of the window comparator, a generated to truncate the gh signal. this causes inductor current to immediately begin decreasing to the new load level. the gh signal will continue to be blanked until the output voltage falls below the high limit. again, since the output voltage pled at four times the switching frequency, over shoot will be decreased and the time required to get back into the regulation band is also decreased.
? 2014 exar corporation ovs can be used in conjunction with both the pwm and pfm operating modes. when it is activated it can no ticeably decrease output voltage excursions when transitioning between pwm and pfm modes. i nternal d rivers the internal high and low gate drivers use totem pole fets for high drive capability. they are powered by two external 5v power pins (vccd1-2) and (vccd3- 4), vccd1 the drivers for channels 1 and 2 and vccd3 powers channels 3 and 4. the drivers can be powered by the internal 5v ldo by connecting their power pins to the ldo5 output through an rc filter to avoid conducted noise back into the analog circuitry. to minimize power dissipation in the 5v ldo it is recommended to power the drivers from an external 5v power source either directly or by using the v5ext input. good quality 1uf to 4.7uf capacitors should be connected directly between the power pins to ground to optimize driver performance and minimize noise coupling to the 5v ldo supply. the driver outputs should be connected directly to their corresponding output switching fets, with the lx output connected to the drain of the lower fet for the best current monitoring accuracy. see anp-32 practical layout guidelines for power xr designs. ldo s the xrp7725 has two internal low drop out (ldo) linear regulators that generate 5.0v i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 17/34 ovs can be used in conjunction with both the pwm and pfm operating modes. when it is ticeably decrease output voltage excursions when transitioning between the internal high and low gate drivers use totem pole fets for high drive capability. they are powered by two external 5v power pins 4), vccd1 -2 powers the drivers for channels 1 and 2 and vccd3 -4 powers channels 3 and 4. the drivers can be powered by the internal 5v ldo by connecting their power pins to the ldo5 output through an rc filter to avoid conducted noise back into to minimize power dissipation in the 5v ldo it is recommended to power the drivers from an external 5v power source either directly or by using the v5ext input. good quality 1uf to 4.7uf capacitors should be connected directly the power pins to ground to optimize driver performance and minimize noise the driver outputs should be connected directly to their corresponding output switching fets, with the lx output connected fet for the best practical layout guidelines for has two internal low drop out (ldo) linear regulators that generate 5.0v (ldo5) and 3.3v (ldo3_3) for both internal and external use. additionally it also has a 1.8v regulator that supplies power for the xrp7725 internal circuits. block diagram of the linear power supplies. ldo5 is the main power input to the device and is supplied by an external 5.5v to 25v (v cc ) supply. the output of ldo5 should be bypassed by a good quality capacitor connected between the pin and ground close to the device. the 5v output is used by the xrp7725 as a standby power supply and is also used to power the 3.3v and 1.8v linear regulators inside the chip and can also supply power to the 5v gate drivers. the total output current that the 5v ldo can provide is 130ma. the xrp7725 consumes approximately 20ma and the rest is shared between ldo3_3 and the gate drive currents. during initial po up, the maximum external load should be limited to 30ma. the 3.3v ldo output available on the ldo3_3 pin is solely for customer use and is not used internally. this supply may be turned on or off by the configuration registers. again a good bypass capa citor should be used. the avd d pin is the 1.8v regulator output and needs to be connected externally to the dv pin on the device. a good quality capacitor should be connected between this pin and ground close to the package. for operation with a v cc of 4.75v to 5.5v, the ldo5 output needs to be connected directly to v cc on the board. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 (ldo5) and 3.3v (ldo3_3) for both internal use. additionally it also has a 1.8v regulator that supplies power for the internal circuits. figure 3 shows a block diagram of the linear power supplies. ldo5 is the main power input to the device and is supplied by an external 5.5v to 25v supply. the output of ldo5 should be bypassed by a good quality capacitor connected between the pin and ground close to the device. the 5v output is used by the as a standby power supply and is also used to power the 3.3v and 1.8v linear inside the chip and can also supply power to the 5v gate drivers. the total output current that the 5v ldo can provide is 130ma. consumes approximately 20ma and the rest is shared between ldo3_3 and during initial po wer up, the maximum external load should be the 3.3v ldo output available on the ldo3_3 pin is solely for customer use and is not used internally. this supply may be turned on or off by the configuration registers. again a good citor should be used. d pin is the 1.8v regulator output and needs to be connected externally to the dv dd pin on the device. a good quality capacitor should be connected between this pin and ground close to the package. of 4.75v to 5.5v, the ldo5 output needs to be connected directly to
? 2014 exar corporation c locks and t iming pll x4/x8 reg ext clock input gpio0 4/ 8 reg clock divider frequency set reg system clock figure figure 18 shows a simplified block di the xrp7725 timing. again, please note that the function blocks and signal names used are chosen for ease of understanding and do not necessarily reflect the actual design. the system timing is generated by a 103mhz internal system clock (sys_clk) . there are two ways that the 103mhz system clock can be generated. these include an internal oscillator and a phase locked loop (pll) that is synchronized to an external clock input. the basic timing architecture is to divide the sys_clk down to create a fundamental switching frequency (fsw_fund) for all the output channels that is settable from 1 to 306khz. the switching frequency for a channel (fsw_chx) can then be selected as 1 time, 2 times or 4 times the fundamental switching frequency. to set t he base frequency for the output channels, an fsw_set value representing the base frequency shown in table 1, is entered into the switching frequency configuration register. note that fsw_set value is basically equal to the sys_clk divided by the base fr equency. the system timing is then created by dividing down sys_clk to produce a base frequency clock, 2x and 4x times the base frequency clocks, and sequencing timing to position the output channels relative to each other. each output i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 18/34 clock divider ext clock output gpio1 frequency set reg dpwm to channels 2 4 system clock base frequency 2x 4x freg mult reg sel sequencer figure 18: xrp7725 timing block diagram shows a simplified block di agram of timing. again, please note that the function blocks and signal names used are chosen for ease of understanding and do not necessarily reflect the actual design. the system timing is generated by a 103mhz . there are two ways that the 103mhz system clock can be generated. these include an internal oscillator and a phase locked loop (pll) that is synchronized to an external clock input. the basic timing architecture is to divide the fundamental switching frequency (fsw_fund) for all the output channels that is settable from 1 05khz to 306khz. the switching frequency for a channel (fsw_chx) can then be selected as 1 time, 2 times or 4 times the fundamental he base frequency for the output channels, an fsw_set value representing the base frequency shown in table 1, is entered into the switching frequency note that fsw_set value is basically equal to the sys_clk divided equency. the system timing is then created by dividing down sys_clk to produce a base frequency clock, 2x and 4x times the base frequency clocks, and sequencing timing to position the output channels relative to each other. each output channel then has its own frequency multiplier register that is used to select its final output switching frequency. table 1 shows the available channel switching frequencies for the xrp7725 practice the powerarchitect? 5.1 (pa 5.1) design tool handles all the detai user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency multiplier for each channel. if an external clock is used, the frequencies in this table will shift accordingly. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 ch1 timing freg mult reg own frequency multiplier register that is used to select its final output table 1 shows the available channel switching xrp7725 device. in practice the powerarchitect? 5.1 (pa 5.1) design tool handles all the detai ls and the user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency multiplier for each channel. if an external clock is used, the frequencies in this table will shift accordingly.
? 2014 exar corporation base frequency khz available 2x frequencies khz available 4x frequencies 105.5 211.1 107.3 214.6 109.1 218.2 111.0 222.0 112.9 225.9 115.0 229.9 117.0 234.1 119.2 238.4 121.5 242.9 123.8 247.6 126.2 252.5 128.8 257.5 131.4 262.8 134.1 268.2 137.0 273.9 139.9 279.9 143.1 286.1 146.3 292.6 149.7 299.4 153.3 306.5 157.0 314.0 160.9 321.9 165.1 330.1 169.4 338.8 174.0 348.0 178.8 357.6 183.9 367.9 189.3 378.7 195.1 390.2 201.2 402.3 207.7 415.3 214.6 429.2 222.0 444.0 229.9 459.8 238.4 476.9 247.6 495.2 257.5 515.0 268.2 536.5 279.9 559.8 292.6 585.2 306.5 613.1 table 1 i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 19/34 available 4x frequencies khz 422.1 429.2 436.4 444.0 451.8 459.8 468.2 476.9 485.8 495.2 504.9 515.0 525.5 536.5 547.9 559.8 572.2 585.2 598.8 613.1 628.0 643.8 660.3 677.6 695.9 715.3 735.7 757.4 780.3 804.7 830.6 858.3 887.9 919.6 953.7 990.4 1030.0 1072.9 1119.6 1170.5 1226.2 x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0
? 2014 exar corporation s upervisory and c ontrol power system design with xrp7725 accomplished using pa 5.1 design tool. all figures referenced in the following sections are taken from pa 5.1. furthermore, the following sections reference i 2 c commands. for more information on these commands, refer to anp-38. d igital i/o xrp7725 has two general purpose input output (gpio) and three power system output (psio) user configurable pins. ? gpios are 3.3v cmos logic compatible and 5v tolerant. ? psios which configured as outputs are open drain and require external pull resistors. th ese i/os are 3.3v and 5v cmos logic compatible, and up to 15v capable. the polarity of the gpio/psio pins is set in pa 5.1 or with an i 2 c command. configuring gpio/psios the following functions can be controlled from or forwarded to any gpio/psio: ? general output C set with an i command ? general input C triggers an interrupt; state read with an i 2 c command i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 20/34 xrp7725 is accomplished using pa 5.1 design tool. all figures referenced in the following sections are taken from pa 5.1. furthermore, the c commands. for more information on these commands, two general purpose input system input output (psio) user configurable pins. gpios are 3.3v cmos logic compatible psios which configured as outputs are open drain and require external pull -up ese i/os are 3.3v and 5v cmos logic compatible, and up to 15v the polarity of the gpio/psio pins is set in the following functions can be controlled from set with an i 2 c triggers an interrupt; c command ? power group enable enabling and d isabling of group 1 and group 2 ? power channel enable enabling and disabling of a individual ch annel including ldo3.3 ? i 2 c address bit C address bit ? power ok C indicates that selected channels have reached their target levels and have not faulted. multiple channel selection is available, in which case the resulting signal is the and logic function of all channels selected ? resetout C is delayed power ok. delay is programmable in 1msec increments with the range of 0 to 255 msecs ? low v cc C indicates when v below the uvlo fault threshold and whe n the uvlo condition clears (v voltage rise s above the uvlo warning level) ? interrupt C the controller gener interrupt selection and clearing is done through i 2 c commands interrupt, low v cc , power ok and resetout signals can only be forwarded to a single gpio/psio. in addition, the following are functions that are unique to gpio0 and gpio1. ? hw flags C these are hardware monitoring functions forwarded to gpio0 only. the functions include under- voltage warning, over temperature warning, over fault, over- current fault and over current warning for every channel. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 power group enable C controls isabling of group 1 and power channel enable C controls enabling and disabling of a individual annel including ldo3.3 C controls an i 2 c indicates that selected channels have reached their target levels and have not faulted. multiple channel selection is available, in which case the resulting signal is the and logic function of all channels selected is delayed power ok. delay is programmable in 1msec increments with the range of 0 to 255 msecs indicates when v cc has fallen below the uvlo fault threshold and n the uvlo condition clears (v cc s above the uvlo warning the controller gener ated interrupt selection and clearing is done c commands , power ok and resetout signals can only be forwarded to a single in addition, the following are functions that are unique to gpio0 and gpio1. these are hardware monitoring functions forwarded to gpio0 only. the functions include voltage warning, over - temperature warning, over -voltage current fault and over - current warning for every channel.
? 2014 exar corporation multiple selections will be combi using the or logic function. ? external clock-in C enables the controller to lock to an external clock including one from another applied to the gpio0 pin. there are two ranges of clock frequencies the controller accepts, selectable by a user. ? hw power good C the power good hardware monitoring function. it can only be forwarded to gpio1. this is an output voltage monitoring function that is a hardware comparison of channel output voltage against its user defined power good threshold limits (po minimum and maximum levels). it has no hysteresis. multiple channel selections will be combined using the and logic function of all channels selected. the power good minimum and maximum levels are expressed as percentages of the target voltage. pgood max is the upper window and pgood min is the lower window. the minimum and maximum for each of these i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 21/34 multiple selections will be combi ned using the or logic function. enables the controller to lock to an external clock including one from another xrp7725 applied to the gpio0 pin. there are two ranges of clock frequencies the controller the power good hardware monitoring function. it can only be forwarded to gpio1. this is an output voltage monitoring function that is a hardware comparison of channel output voltage against its user defined power good threshold limits (po wer good minimum and maximum levels). it has no hysteresis. multiple channel selections will be combined using the and logic function the power good minimum and maximum levels are expressed as percentages of the pgood max is the upper window and pgood min is the lower window. the minimum and maximum for each of these values can be calculated with the following equation:
where n=1 to 63 for the pgood max value and n=1 to 62 for the pgood min value. for example, with the target voltage of 1.5v and set point resolution of 2.5mv (lsb), the power good min and max values can range from 0.17% to 10.3% and 0.17% to 10.5% respectively. a user can effectively do changing to the next higher output voltage range setting, but at the expense of reduced set point resolution. ? external clock-out through gpio1 for synchronizing with another xrp7725 (see the clock out section for more inf ormation). f ault h andling there are seven different types of fault handling: ? under voltage lockout (uvlo) mo nitors voltage supplied to the and will cause the controller to shut down all channels if the supply drops to critical levels. ? over temperature protection (otp) monitors temperature of the chip and will cause the controller to shut down all channels if temperature rises to critical levels. ? over voltage protection (ovp) monitors regulated voltage of a and will cause the controll user specified way if the regulated voltage surpasses threshold level. ? over current protection (ocp) monitors current of a channel and will cause the controller to react in a user specified way if the current level surpasses threshold lev ? start-up time- out fault whether a channel gets into regulation in a user defined time period ? ldo5 over current protection (ldo5 ocp) monitors current x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 values can be calculated with the following
where n=1 to 63 for the pgood max value and n=1 to 62 for the pgood min value. for example, with the target voltage of 1.5v and set point resolution of 2.5mv (lsb), the power good min and max values can range from 0.17% to 10.3% and 0.17% to 10.5% respectively. a user can effectively do uble the range by changing to the next higher output voltage range setting, but at the expense of reduced set point resolution. C clock sent out through gpio1 for synchronizing with (see the clock out ormation). different types of fault under voltage lockout (uvlo) nitors voltage supplied to the v cc pin and will cause the controller to shut down all channels if the supply drops to critical temperature protection (otp) monitors temperature of the chip and will cause the controller to shut down all channels if temperature rises to critical over voltage protection (ovp) regulated voltage of a channel and will cause the controll er to react in a user specified way if the regulated voltage surpasses threshold level. over current protection (ocp) monitors current of a channel and will cause the controller to react in a user way if the current level surpasses threshold lev el. out fault monitors a channel gets into regulation in a user defined time period ldo5 over current protection (ldo5 current drawn from the
? 2014 exar corporation regulator and will cause the c be reset if the current exceeds ldo ? ldo3.3 over current protection (ldo3.3 ocp) monitors current from the regulator and will cause the controller to shut down the regulator if the current exceeds ldo3.3 limit uvlo both uvlo warning and fault levels are user programmable and set at 200mv increments in pa 5.1. when the warning level is reached the controller will generate the uvlo_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the digital i/o section). when an un der voltage fault condition occurs, the xrp7725 outputs are shut down and the uvlo_fault_active_event interrupt is generated. in addition, the host can be informed by forwarding the low v any gpio/psio (see the digital i/o section). this signal transitions when the uvlo fault occurs. when com ing out of the fault, rising v cc crossing the uvlo fault level will trigger the uvlo_fault_inactive_event interrupt. once the uvlo condition clears (v rises above or to the user- defined warning level), the low v cc transition and the controller will be reset. special attention needs to be paid in the case when v cc = ldo5 = 4.75v to 5.5v. since the input voltage adc resolution is 200mv, the uvlo warning and fault set points are coar for a 5v input. therefore, setting the warning level at 4.8v and the fault level at 4.6v may result in the outputs not being re until a full 5.0v is reached on v cc . setting the warning level to 4.6v and the fault level at 4.4v would likely make uvlo hand desired; however, at a fault level below 4.6v the device has hardware uvlo on ldo5 to ensure proper shutdown of the internal circuitry of the controller. this means the 4.4v uvlo fault leve l may never occur. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 22/34 c ontroller to if the current exceeds ldo 5 limit ldo3.3 over current protection monitors current drawn the regulator and will cause the controller to shut down the regulator if the both uvlo warning and fault levels are user set at 200mv increments when the warning level is reached the controller will generate the uvlo_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the der voltage fault condition occurs, outputs are shut down and the uvlo_fault_active_event interrupt is generated. in addition, the host can be v cc signal to any gpio/psio (see the digital i/o section). transitions when the uvlo fault ing out of the fault, rising crossing the uvlo fault level will trigger the uvlo_fault_inactive_event interrupt. uvlo condition clears (v cc voltage defined uvlo signal will transition and the controller will be reset. to be paid in the case = ldo5 = 4.75v to 5.5v. since the input voltage adc resolution is 200mv, the uvlo warning and fault set points are coar se for a 5v input. therefore, setting the warning level at 4.8v and the fault level at 4.6v may result in the outputs not being re -enabled . setting the warning level to 4.6v and the fault level at uvlo hand ling as desired; however, at a fault level below 4.6v uvlo on ldo5 to ensure proper shutdown of the internal circuitry of the controller. this means the l may never occur. otp user defined otp warning, levels are set at 5c increments in pa 5.1. when the warning level is reached the controller will generate the temp_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the digital i/o section). when an otp fault condition occurs, the xrp7725 outputs are shut down and the temp_over_event interrupt is generated. once temperature reaches a user defined otp restart threshold level, the temp_under_event interrupt will be generated an d the controller will reset. ovp a user defined ovp fault level is set in pa 5.1 and is expressed in percentages of a regulated target voltage. resolution is the same as for the target voltage (expressed in percentages). the ovp minimum and maximum val by the following equation where the range for n is 1 to 63:
when the ovp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated the controller. the host then can use an i command to check which channel is at fault. in addition, ovp fault can be monitored through gpio0. a user can choose one of three options in response to an ovp event: shut faulting channel, shut dow and perform auto- restart of the channel, or restart the chip. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 user defined otp warning, fault and restart levels are set at 5c increments in pa 5.1. when the warning level is reached the controller will generate the temp_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the when an otp fault condition occurs, the outputs are shut down and the temp_over_event interrupt is generated. once temperature reaches a user defined otp restart threshold level, the temp_under_event interrupt will be d the controller will reset. a user defined ovp fault level is set in pa 5.1 and is expressed in percentages of a resolution is the same as for the target voltage (expressed in percentages). the ovp minimum and maximum val ues are calculated by the following equation where the range for
when the ovp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. in addition, ovp fault can be monitored a user can choose one of three options in response to an ovp event: shut down the faulting channel, shut dow n faulting channel restart of the channel, or
? 2014 exar corporation warning: choosing the restart chip option during development is not recommended as it makes debug efforts difficult. in the case of shutting down the faulting channel and auto- restarting, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for an ovp or ocp event. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 23/34 warning: choosing the restart chip option during development is not recommended as it makes debug efforts in the case of shutting down the faulting restarting, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of note: the channel fault action response is the same for an ovp or ocp event. ocp a user defined ocp fault level is set with 10 ma increments in pa 5.1. pa 5.1 uses calculations to give the user the approximate dc output current entered in the current limit field. however the actual current limit trip value programmed into the part is 280mv as defined in the electrical characteristics. the maximum value the user can program is limited by synchronous power fet and current monitoring adc range. for example, using a synchronous fet with r dson wider adc range, the maximum current limit programmed would be: the current is sampled approximately 30ns before the low side mosfet turns off, so the actual measured dc output current in this example would be 9.33a plus ap half the inductor ripple. an ocp fault is considered to have occurred only if the fault threshold has been tripped in four consecutive switching cycles. when the switching frequency is set to the 4x multiplier, the current is sampled only ev as a result it can take as many as eight switching cycles for an over current event to be detected. when operating in 4x mode an inductor with a soft saturation characteristic is recommended. when the ocp level is reached and the fault i generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i command to check which channel is at fault. in addition, ocp faults can be monitored through hw flags on gpio0. the host ca also monitor the ocp warning flag through hw flags on gpio0. the ocp warning level is calculated by pa 5.1 as 85% of the ocp fault level. a user can choose one of three options in response to an ocp event: shut faulting channel, shut down faulti x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 a user defined ocp fault level is set with 10 ma increments in pa 5.1. pa 5.1 uses calculations to give the user the approximate dc output current entered in the current limit field. however the actual current limit trip value programmed into the part is limited to 280mv as defined in the electrical characteristics. the maximum value the user can program is limited by r dson of the synchronous power fet and current monitoring adc range. for example, using a dson of 30mx, and the adc range, the maximum current limit !" the current is sampled approximately 30ns before the low side mosfet turns off, so the actual measured dc output current in this example would be 9.33a plus ap proximately an ocp fault is considered to have occurred only if the fault threshold has been tripped in four consecutive switching cycles. when the switching frequency is set to the 4x multiplier, the current is sampled only ev ery other cycle. as a result it can take as many as eight switching cycles for an over current event to be detected. when operating in 4x mode an inductor with a soft saturation characteristic is when the ocp level is reached and the fault i s generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. in addition, ocp faults can be monitored through hw flags on gpio0. the host ca n also monitor the ocp warning flag through hw flags on gpio0. the ocp warning level is calculated by pa 5.1 as 85% of the ocp fault a user can choose one of three options in response to an ocp event: shut down the faulting channel, shut down faulti ng channel
? 2014 exar corporation and perform auto- restart of the channel, or restart the chip. warning: choosing the restart chip option during development is not recommended as it makes debug efforts difficult. the output current reported by the is processed through a seven sample median filter in order to reduce noise. the ocp limit is compared against unfiltered adc output. for the case of shutdown and auto channel, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for an ovp or ocp event. start-up time-out fault a channel will be at startup timeout fault if it does not come- up in the time period specified in the startup timeout box. in addition, a channel is at startup timeout fault if its pre bias configuration voltage is within a defined value too close to the target. when the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 24/34 restart of the channel, or warning: choosing the restart chip option during development is not recommended as it makes debug efforts the output current reported by the xrp7725 a seven sample median filter in order to reduce noise. the ocp limit is compared against unfiltered adc output. for the case of shutdown and auto -restart channel, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for an ovp or ocp event. a channel will be at startup timeout fault if it up in the time period specified in the startup timeout box. in addition, a channel is at startup timeout fault if its pre - bias configuration voltage is within a defined when the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the c command to check ldo5 ocp when current is drawn from the l exceeds the ldo5 current limit the controller will be reset. ldo3.3 ocp when current drawn from ldo3.3 exceeds ldo3.3 current limit the regulator gets shut down, a fault is generated, and the host will be notified by the supply_fault_event interru pt generated by the controller. the host then can through an i which channel/regulator is at fault. once the fault condition is removed, the host needs to turn the regulator on again. v5ext switchover the v5ext gives a user an opportunity t supply an external 5 volt rail to the controller in order to reduce the controllers power dissipation. the 5 volt rail can be an independent power rail present in a system or any of 7725 channels regulated to 5 volts (in the pfm mode in particular) and to the v5ext pin. it is important to mention that voltage to v cc must be applied all the time even after the switchover in which case the current drawn from minimal. if the function not used, we recommend the pin to be eithe r grounded or left floating in conjunction with making sure the function gets disabled through register settings. v5ext switchover control the function is enabled in pa 5.1. the switchover thresholds are programmable in 50mv steps with a total range of 20 hysteresis to switch the external 5 supply in- out is 150mv. ldo5 automatically turns off when the external voltage is switched in and turns on when the external voltage drops below the lower threshold. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 when current is drawn from the l do5 that exceeds the ldo5 current limit the controller when current drawn from ldo3.3 exceeds ldo3.3 current limit the regulator gets shut down, a fault is generated, and the host will be notified by the supply_fault_event pt generated by the controller. the host then can through an i 2 c command check which channel/regulator is at fault. once the fault condition is removed, the host needs to turn the regulator on again. the v5ext gives a user an opportunity t o supply an external 5 volt rail to the controller in order to reduce the controllers power dissipation. the 5 volt rail can be an independent power rail present in a system or any of 7725 channels regulated to 5 volts (in the pfm mode in particular) and routed back to the v5ext pin. it is important to mention must be applied all the time even after the switchover in which case the current drawn from v cc supply will be if the function not used, we recommend the r grounded or left floating in conjunction with making sure the function gets disabled through register settings. v5ext switchover control the function is enabled in pa 5.1. the switchover thresholds are programmable in 50mv steps with a total range of 20 0mv. hysteresis to switch the external 5 volt out is 150mv. ldo5 automatically turns off when the external voltage is switched in and turns on when the external voltage drops below the lower threshold.
? 2014 exar corporation when the controller switches over to the v 5ext rail, the v5ext_rise interrupt is generated to inform the host. similarly, when the controller switches out, the v5ext_fall interrupt gets generated. e xternal clock synchr onization xrp7725 can be run off an external clock available in the system or another the external clock must be in the ranges of 10.9mhz to 14.7mhz or 21.8mhz to 29.6mhz. locking to the external clock is done through an internal phase lock loop (pll) requir es an external loop capacitor of 2.2nf be connected between the cpll pin and agnd. in applications where this functionality is not desired, the cpll capacitor is not necessary and can be omitted, and the pin shall be left floating. in addition, the user needs to make sure the function gets disabled through register settings. the external clock must be routed to gpio0. the gpio0 setting must reflect the range of the external clock applied to it: sys_clock/8 corresponds to the range of 10.9mhz to 14.7mh z while sys_clock/4 setting corresponds to the range of 21.8mhz to 29.6mhz. the functionality is enabled in pa 5.1 by selecting external clock- in function under gpio0. for more details on how to monitor pll lock in- out, please contact exar or your local representative. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 25/34 when the controller switches over to the 5ext rail, the v5ext_rise interrupt is generated to inform the host. similarly, when the controller switches out, the v5ext_fall onization can be run off an external clock available in the system or another xrp7725. the external clock must be in the ranges of 10.9mhz to 14.7mhz or 21.8mhz to 29.6mhz. locking to the external clock is done through an internal phase lock loop (pll) which es an external loop capacitor of 2.2nf to be connected between the cpll pin and in applications where this functionality is not desired, the cpll capacitor is not necessary and can be omitted, and the pin shall be left needs to make sure the function gets disabled through the external clock must be routed to gpio0. the gpio0 setting must reflect the range of the external clock applied to it: sys_clock/8 corresponds to the range of 10.9mhz to z while sys_clock/4 setting corresponds to the range of 21.8mhz to the functionality is enabled in pa 5.1 by in function under for more details on how to monitor pll lock out, please contact exar or your local exar c lock o ut xrp7725 can supply clock out to be used by another xrp7725 controller. the clock is routed out through gpio1 and can be set to system clock divided by 8 (sys_clock/8) or system clock divided by 4 (sys_clock/4) frequencies. the functionality is enabled in pa 5.1 by selecting external clock- out function under gpio1. c hannel c ontrol channels including ldo3.3 independently by any gpio/psio or i command. channels will start down following transi tions of signals applied to gpio/psios set to control the channels. the control can always be overridden with an i 2 c command. regardless of whether the channels are controlled independently or are in a group, the ramp rates will be followed as specified ( see the power sequencing section). regulated voltages and voltage drops across the synchronous fet on each switching channel can be read back using i commands. the regulated voltage read back resolution is 15mv, 30mv and 60mv per lsb depending on the ta rget voltage range. the voltage drop across synchronous fet read back resolution is 1.25mv and 2.5mv per lsb depending on the range. through an i 2 c command the host can check the status of the channels; whether they are in regulation or at fault. regula ted voltages can be dynamically changed on switching channels using i x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 can supply clock out to be used by controller. the clock is routed out through gpio1 and can be set to system clock divided by 8 (sys_clock/8) or system clock divided by 4 (sys_clock/4) the functionality is enabled in pa 5.1 by out function under including ldo3.3 can be controlled independently by any gpio/psio or i 2 c command. channels will start -up or shut- tions of signals applied to gpio/psios set to control the channels. the control can always be overridden with an regardless of whether the channels are controlled independently or are in a group, the ramp rates will be followed as specified see the power sequencing section). regulated voltages and voltage drops across the synchronous fet on each switching channel can be read back using i 2 c commands. the regulated voltage read back resolution is 15mv, 30mv and 60mv per lsb rget voltage range. the voltage drop across synchronous fet read back resolution is 1.25mv and 2.5mv per lsb depending on the range. c command the host can check the status of the channels; whether they are ted voltages can be dynamically changed on switching channels using i 2 c
? 2014 exar corporation commands with resolution of 2.5mv, 5mv and 10mv depending on the target voltage range (in pwm mode only). for more information on i 2 c commands please refer to anp- 38 or contact exar or your local exar representative. p ower s equencing all four channels and ldo3.3 can be grouped together and will start- up and shut user defined sequence. selecting none means channel(s) assigned to any group and therefore will be controlled independently. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 26/34 commands with resolution of 2.5mv, 5mv and 10mv depending on the target voltage c commands 38 or contact exar or can be grouped up and shut -down in a will not be assigned to any group and therefore will be group selection there are three groups: ? group 0 C is controlled by the chip enable or an i 2 c command. channels assigned to this group will come up with the enable sign al being high (plus additional delay needed to load configuration from flash to run registers), and will go down with the enable signal being low. the control can always be overridden with an i command since it is recommended to leave the enable pin floating in the applications when v cc = ldo5 = 4.75v to 5.5v, please contact exar for how to configure the channels to come up a this scenario ? group 1 C can be controlled by any gpio/psio or i 2 c command. assigned to this group will start shut- down following transitions of a signal applied to the gpio/ psio set to control the group. the control can always be overridden with an i 2 c command ? group 2 C can be controlled by any gpio/psio or i 2 c command. assigned to this group will start shut- down following transitions of a signal applied to the gpio/psio set to control the group. the control can always be overridden with an i 2 c command start-up for each channel withi n a group, a user can specify the following start - ? ramp rate C expressed in milliseconds per volt. it does not apply to ldo3.3 x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 is controlled by the chip c command. channels assigned to this group will come up with al being high (plus additional delay needed to load configuration from flash to run -time registers), and will go down with the enable signal being low. the control can always be overridden with an i 2 c since it is recommended to leave the enable pin floating in the applications = ldo5 = 4.75v to 5.5v, please contact exar for how to configure the channels to come up a t the power up in can be controlled by any c command. channels assigned to this group will start -up or down following transitions of a signal psio set to control the group. the control can always be c command can be controlled by any c command. channels assigned to this group will start -up or down following transitions of a signal applied to the gpio/psio set to control the group. the control can always be c command n a group, a user can - up characteristics: expressed in milliseconds does not apply to ldo3.3
? 2014 exar corporation ? order C position of a channel to come within the group ? wait pgood? C selecting this option for a channel m eans the next channel in the order will not start ramping- up until this channel reaches the target level and power good flag is asserted ? delay C an additional time delay a user can specify to postpone a channel start with respect to the previous cha order. the delay is expressed in milliseconds w ith a range of 0msec to 255msec shut-down for each channel within a group a user can specify the following shut characteristics: ? ramp rate C expressed in milliseconds per volt. it does not apply to ldo3 ? order C position of a channel to come down within the group ? wait stop thresh? C selecting this option for a channel means the next channel in the order will not start ramping- down until this channel reaches the stop threshold level. the sto threshold le vel is fixed at 600mv ? delay C additional time delay a user can specify to postpone a channel shut with respect to the previous channel in the order. the delay is expressed in milliseconds w ith a range of 0msec to 255msec m onitoring v cc and t emperature through i 2 c commands, the host can read back the voltage applied to the v the die temperature respectively. the read back resolution is 200mv per lsb; the die temperature read back resolution is 5c per lsb. for more on i 2 c com mands please refer to anp-38. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 27/34 position of a channel to come -up selecting this option for eans the next channel in the up until this channel reaches the target level and its an additional time delay a user can specify to postpone a channel start -up with respect to the previous cha nnel in the order. the delay is expressed in ith a range of 0msec to for each channel within a group a user can specify the following shut -down expressed in milliseconds apply to ldo3 .3 position of a channel to come - selecting this option for a channel means the next channel in the order will not start down until this channel reaches the stop threshold level. the sto p vel is fixed at 600mv additional time delay a user can specify to postpone a channel shut -down with respect to the previous channel in the order. the delay is expressed in ith a range of 0msec to emperature c commands, the host can read v cc pin and the die temperature respectively. the v cc read back resolution is 200mv per lsb; the die temperature read back resolution is 5c mands please i nstantaneous c urrent xrp7725 will capture v 1msec on all channels until a user defined sample threshold is reached. then, the sum is latched into a separate register to be read from an i 2 c command. the sample size is selected in power architect 5.1 (pa 5.1). the recommended maximum sample size is 512. going over this limit could potentially cause overflow. in certain design it would be possible to increase sample size above this limit without problems depend on the design parameters. if there is such a need please contact exar representatives who will determine if your design is suitable. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 urrent m onitoring xrp7725 will capture v il readings every 1msec on all channels until a user defined sample threshold is reached. then, the sum is latched into a separate register to be read the sample size is selected in power architect the recommended maximum sample size is 512. going over this limit could cause overflow. in certain design s it would be possible to increase sample size above this limit without problems , but this will depend on the design parameters. if there is such a need please contact exar representatives who will determine if your
? 2014 exar corporation the host should ti me its reading frequency to match the sample window size. a gpio/psio can be configured in pa 5.1 to indicate to the host each time a new accumulated sum has been latched. the io will be asserted after all samples have been taken and held while the ac values are being latched. reading of the accumulated sum is done using following i 2 c commands: 0x71 (vil_acc_read_ch1) C ch1 a ccumulator 0x72 (vil_acc_read_ch2) C ch2 a ccumulator 0x73 (vil_acc_read_ch3) C ch3 a ccumulator 0x74 (vil_acc_read_ch4) C ch4 a ccumulator i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 28/34 me its reading frequency to match the sample window size. a gpio/psio 5.1 to indicate to the accumulated sum has the io will be asserted after all samples have been taken and held while the ac cumulated reading of the accumulated sum is done ccumulator ccumulator ccumulator ccumulator the internal counter can be re reading from the following i 0x70 (vil_acc_init) C accumulator initialization these i 2 c commands follow the same command structure as described in anp-38. once the host reads the accumulated sum, it will need to do some post data processing in order to get an average load current. first, the host has to divide the read sum by a number of samples to obtain an average v register value. secondly, the average v needs to be translated into a load current. translating average v il into a load current to adjust for the gain and offset of the sense circuit the average v il register value be converted to v il . that can be the following equation: ( _ = = ? ife r dec v v v il lx rtn gl equation 1 where ife_gain is a gain setting of the sense circuit. the ife_gain equals to 8 if gain 8 of the sense circuit is enabled, else ife_gain is 4. pa 5.1 sets the gain based on r values entered, and current sense adc range. the ife_gain value can be obtained by reading register 0xd016 via the pa poke function. this is a four bit register with following bit description: bit 0 C ife_gain 8 setting for channel 1 bit 1 C ife_gain 8 setting f or channel 2 bit 2 C ife_gain 8 setting for channel 3 bit 3 C ife_gain 8 setting for channel 4 value 1 indicates gain 8 setting while value 0 indicates gain 4. reading this register from customer software requires implementation of i comman d structure described in anp x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 the internal counter can be re initialized by the following i 2 c command: accumulator initialization c commands follow the same command structure as the commands reads the accumulated sum, it will need to do some post data processing in order to get an average load current. first, the host has to divide the read sum by a number of samples to obtain an average v il secondly, the average v il register value needs to be translated into a load current. il register value to adjust for the gain and offset of the sense register value needs to . that can be done with ) 04.0 _ 01.0 * _ ? gain ife value r equation 1 where ife_gain is a gain setting of the sense circuit. the ife_gain equals to 8 if gain 8 of the sense circuit is enabled, else ife_gain is sets the gain based on r dson , i outmax and current sense adc range. the ife_gain value can be obtained by reading register 0xd016 via the pa 5.1 peek poke function. this is a four bit register with 8 setting for channel 1 or channel 2 8 setting for channel 3 8 setting for channel 4 value 1 indicates gain 8 setting while value 0 reading this register from customer software requires implementation of i 2 c register read d structure described in anp -39.
? 2014 exar corporation the flash equivalent of this register is 0x if obtaining the value fro m flash hex image is preferred. since v il is a voltage sensed across synchronous power fet during its on time, the current through will be: dson il r v i = equation 2 where r dson is channel resistance of the synchronous power fet entered as a channel parameter in pa 5.1. in addition, xrp7725 samples v il the inductor current which means one half of the inductor ripple current has to be added to current in equation 2 in order to get an average inductor current (load current). inductor ripple current is calculated as: ( ) ( f v v v i sw in out in ripple peak peak * * * ? = ? ? equation 3 where v in , v out , f sw and l are channel parameters entered in pa 5.1. finally, the load current is a sum of the valley current (equation 2) and one half of the inductor ripple current (equation 3). 2 ripple peak peak lvalley load i i i ? ? + = equation 4 note: the calculated load current is dependent on parameters entered in pa r dson and l are the most significant since they will change noticeably depending on operating conditions. because of this, calibrating r dson and l can greatly improve accuracy. for more on r dson and l calibration techniques refer to anp-43. xrp7725 t elemetry in pa 5.1 pa 5.1 adds a new function under the dashboard called xrp7725 telemetry. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 29/34 flash equivalent of this register is 0x 156 m flash hex image is is a voltage sensed across synchronous power fet during its on time, is channel resistance of the synchronous power fet entered as a channel at valley of the inductor current which means one half of the inductor ripple current has to be added to current in equation 2 in order to get an average inductor current (load current). inductor ripple current is calculated as: ) l v out * and l are channel finally, the load current is a sum of the valley current (equation 2) and one half of the (equation 3). ripple the calculated load current is dependent on parameters entered in pa 5.1. and l are the most significant since they will change noticeably depending on operating conditions. because of this, can greatly improve and l calibration 5.1 pa 5.1 adds a new function under the dashboard called xrp7725 telemetry. the function displays load currents calculated as described in the sect ion above. in addition it gives a user an opportunity to mak adjustments to r dson (k r ) and ripple current offset (k o ). the default value of k r calculate k o based on entered design parameters such as v in , v calculated k o can be recalled choose suggested k o . once the design has been calibrated, saving the project file (.pwrxr) will for later use as well. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 the function displays load currents calculated ion above. in addition , it gives a user an opportunity to mak e ) and ripple current is 1. pa 5.1 will based on entered design , v out , f sw and l. the be recalled by clicking on the design has been calibrated, saving will save k r and k o
? 2014 exar corporation the scale and sample values will always reflect what is sav ed in a project file. pa 5.1 will also read actual register value s discrepancies highlighted in red if during design development. c urrent r eading a ccuracy an i mportant advantage of averaging current readings across a large sample size distribution gets much tighter c ompared to current reading through i 2 c bus in xrp7724. the accuracy specification in the electrical table includes quantization noise. quantization noise is divided down by the square root of the number of samples taken by the accumulator. for example, i samples are taken, the quantization noise is reduced by a factor of 20. th e result below shows how the current reading is much improved whether the noise is from the board or quantization noise. p rogramming xrp7725 xrp7725 is a flash based device means its configuration can be programmed into flash nvm and re- programmed a number of times. programming of flash nvm is done through pa 5.1. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 30/34 will always ed in a project file. pa 5.1 s and report in red if there exist mportant advantage of averaging current size is that a ompared to c bus in xrp7724. the accuracy specification in the electrical table includes quantization noise. quantization noise is divided down by the square root of the number of samples taken by the accumulator. for example, i f 400 samples are taken, the quantization noise is e result below shows how the current reading is much from the board is a flash based device which means its configuration can be programmed programmed a programming of flash nvm is done through by clicking on the flash button, user will start programming sequence of the design configuration into the flash nvm. after the programming sequence completes, the chip will reset (if a utomatically reset after flashing box is checked), and boot the design configuration from the flash. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 by clicking on the flash button, user will start programming sequence of the design configuration into the flash nvm. after the programming sequence completes, the chip utomatically reset after flashing box is checked), and boot the design configuration from the flash.
? 2014 exar corporation for users that wish to create their own programming procedure so they can re program flash in- circuit using their system software, please contact exar for a list of i flash commands needed. e nabling xrp7725 xrp7725 has a weak internal pull- up ensuring it gets enabled as soon as internal voltage supplies have ramped up and are in regulation. driving the enable pin low externally will keep the controller in the shut- down mode. a simple open drain pull down is the recommende d way to shut xrp772 if the enable pin is driven high externally to control xrp7725 coming out of the shut mode, care must be taken in such a scenario to ensure the enable pin is driven high after v cc gets supplied to the controller. in the configuration when v cc = ldo5 = 4.75v to 5.5v, disabling the device by grounding the enable pin is not recommended. at this time we recommend leaving the enable pin floating and placing the controller in the standby mode instead in this scenario. the standb y mode is defined as the state when all switching channels and ldo3.3 are disabled, all gpio/psios are programmed as inputs, and system clock is disabled. in this state chip consumes 440ua typical. i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 31/34 for users that wish to create their own programming procedure so they can re - circuit using their system for a list of i 2 c up ensuring it gets enabled as soon as internal voltage supplies have ramped up and are in driving the enable pin low externally will keep down mode. a simple open drain pull down is the d way to shut xrp772 5 down. if the enable pin is driven high externally to coming out of the shut -down mode, care must be taken in such a scenario to ensure the enable pin is driven high after = ldo5 = 4.75v to 5.5v, disabling the device by grounding the enable pin is not recommended. at this time we recommend leaving the enable pin floating and placing the controller in the standby mode instead in y mode is defined as the state when all switching channels and ldo3.3 are disabled, all gpio/psios are programmed as inputs, and system clock is disabled. in this state chip consumes 440ua short duration enable pin toggled low short duration shutd own pulses to the enable pin of the xrp772 provide sufficient time for the ldo5 voltage to fall below 3.5v, can result in significant delay in re- enabling of the device. some examples below show ldo5 and enable pins: no load on ldo5, blue trace. recovery time after enable logic high is approximately 40ms. adding a 200 ohm load on ldo5 pulls voltage below 3.5v and restart is short. note that as v cc increases, the restart time falls as well. 5.5v input is shown as the worst case. since the enable pin has an internal current source, a simple open drain pull down is the recommended way to shut down the x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 short duration enable pin toggled low own pulses to the enable pin of the xrp772 5, which do not provide sufficient time for the ldo5 voltage can result in significant enabling of the device. some examples below show ldo5 and enable trace. recovery time after enable logic high is approximately ohm load on ldo5 pulls voltage below 3.5v and restart is short. increases, the restart time falls as well. 5.5v input is shown as the worst since the enable pin has an internal current source, a simple open drain pull down is the recommended way to shut down the
? 2014 exar corporation xrp7725 . a diode in series with a resistor between the ldo5 and enable pins may offer a wa y to more quickly pull down the ldo5 outpu t when the enable pin is pulled low. application informat ion t hermal d esign as a four channel controller with internal mosfet drivers and 5v gate drive supply all in one 7x7mm 44pin tqfn package, there is the potential for the power dissipation to exceed the package thermal limitations. the xrp7725 has an internal ldo which supplies 5v to the internal circuitry and mosfet drivers during startup. it is generally expected that either one of the switching regulator outputs is 5v or an other 5v rail is available in the system and connected to the 5 volt ext pin. if there is no 5v available in i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 32/34 . a diode in series with a resistor between the ldo5 and enable pins may y to more quickly pull down the t when the enable pin is pulled ion channel controller with internal mosfet drivers and 5v gate drive supply all in one 7x7mm 44pin tqfn package, there is dissipation to exceed the package thermal limitations. the has an internal ldo which supplies 5v to the internal circuitry and mosfet drivers during startup. it is generally expected that either one of the switching other 5v rail is the system and connected to the ext pin. if there is no 5v available in the system, then the power loss will increase significantly and proper thermal design becomes critical. for lower power levels using properly siz ed mosfets, the use of the internal 5v regulator as a gate drive supply is considered appropriate. layout guidelines refer to application note anp layout gu idelines for power anp-35 xrp77xx: extending the mosfet gate drive conductors. x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 the system, then the power loss will increase significantly and proper thermal design becomes critical. for lower power levels ed mosfets, the use of the internal 5v regulator as a gate drive supply is to application note anp -32 practical idelines for power xr designs and xrp77xx: extending the mosfet
? 2014 exar corporation package specification i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 33/34 44- pin 7x7mm tqfn x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 pin 7x7mm tqfn
? 2014 exar corporation revision history revision date 1.0.0 01/27/2014 initia l release [ecn# 14 for further assistance email: exar technical documentation: notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar corporation assume s no responsibility for the use of any circuits des cribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts a nd schedules contained herein are only for illustra tion purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however is assumed for inaccuracies. exar corporation does not recommend the use of any of it s products in life support applications where the f ailure or malfunction of the product can reasonably be expect ed to cause failure of the life support system or t o significantly affect safety or effec tiveness. products are not authorized for use in su ch applications unless exar corporation receives, i n writing, assurances to its satisfaction that: (a) t he risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential li ability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited i i n n t t e e l l n n o o d d e e m m a a n n a a g g e e r r c c o o m m p p a a t t i i b b l l e e p p o o w w e e r r m m a a n n a a 34/34 description l release [ecn# 14 06-03] customersupport@exar.com powertechsupport@exar.com http://www.exar.com/techdoc/default.aspx? e xar c orporation h eadquarters and s ales 48720 kato road fremont, ca 94538 C usa tel.: +1 (510) 668-7000 fax: +1 (510) 668-7030 www.exar.com exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve performance or reliability. exar corporation assume s no responsibility for the use of any circuits des cribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent nd schedules contained herein are only for illustra tion purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however corporation does not recommend the use of any of it s products in life support applications where the f ailure or malfunction of the product can reasonably be expect ed to cause failure of the life support system or t o significantly affect tiveness. products are not authorized for use in su ch applications unless exar corporation receives, i n writing, assurances to its satisfaction that: (a) t he risk of injury or damage has been minimized; (b) the user assumes all ability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited . x x r r p p 7 7 7 7 2 2 5 5 e e p p r r o o g g r r a a m m m m a a b b l l e e a a g g e e m m e e n n t t s s y y s s t t e e m m rev. 1.0.0 powertechsupport@exar.com http://www.exar.com/techdoc/default.aspx? ales o ffices exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve performance or reliability. exar corporation assume s no responsibility for the use of any circuits des cribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent nd schedules contained herein are only for illustra tion purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however , corporation does not recommend the use of any of it s products in life support applications where the f ailure or malfunction of the product can reasonably be expect ed to cause failure of the life support system or t o significantly affect its tiveness. products are not authorized for use in su ch applications unless exar corporation receives, i n writing, assurances to its satisfaction that: (a) t he risk of injury or damage has been minimized; (b) the user assumes all ability of exar corporation is adequately protected under the circumstances.

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